Science Links Japan | Processor architecture and evaluation which correspond to deviation of the memory latency.

Processor architecture and evaluation which correspond to deviation of the memory latency.

Accession number;99A0182301

Title;Processor architecture and evaluation which correspond to deviation of the memory latency.

Author; MITAKE DAISUKE (Tokai Univ., Grad. Sch.) SHIMIZU NAOHIKO (Tokai Univ., Sch. of Eng.)

Journal Title;Joho Shori Gakkai Kenkyu Hokoku

Journal Code:Z0031B

ISSN:0919-6072

VOL.98;NO.115(HPC-74);PAGE.83-88(1998)

Figure&Table&Reference;FIG.9, TBL.1, REF.9

Pub. Country;Japan

Language;Japanese

Abstract;The deviation of the memory latency is hard to predict for software especially on the SMP or NUMA systems. As the correspondence method by hardware, the multi-thread processor has been devised. However, it is not general to improve a performance in a single program. We have been proposed SCALT which has a buffer as a software context. For the deviation of a latency problem, a instruction which checks existence of the data arrival to a buffer has been proposed. This report describes the SCALT and evaluatation results the performance of SCALT with buffer check instruction with an event-driven simulator for SMP system. (author abst.)

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