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Accession number;99A0938085
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| Title;High-Speed Logic LSI System with Eliminating Redundant Calculation. |
| Author;
IMAI MAKOTO
(Tohoku Univ.)
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Journal Title;Record of Electrical and Communication Engineering Conversazione, Tohoku University
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Journal Code:F0511A
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ISSN:0385-7719
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VOL.68;NO.1;PAGE.77-80(1999)
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| Figure&Table&Reference;FIG.8, REF.2 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;We have developed two kind of novel architectures to decrease the redundant calculations automatically. The first architecture employs new digit-serial algorithm which eliminate the redundant lower digit calculations by Most-significant-digit-first(MSD-first) digit-serial calculation scheme. Basic components based on this architecture, which employ redundant number system to limit carry propagation, have been developed. MSD-first sequential vector quantization processor(VQP) exhibits 3.7 times faster than ordinary digital system by eliminating redundant lower-bit calculation. 16*16-bit MSD-first digit-serial multiplier has been also fabricated and its operation is experimentally confirmed. The second architecture decreases the complex calculation steps by excluding the useless data before executing the complex calculations according to the characterized value of data. About 90% of Manhattan-distance(MD) calculations in VQP are excluded by estimating the MD from average-distance. (author abst.) |
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