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Accession number;01A0340299
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| Title;Reducing the loading time of configuration data on multi-context FPGAs. |
| Author;
KITAOKA TOSHIRO
(Keio Univ., Fac. of Sci. and Technol.)
UNO MASAKI
(Keio Univ., Fac. of Sci. and Technol.)
SHIBATA YUICHIRO
(Keio Univ., Fac. of Sci. and Technol.)
AMANO HIDEHARU
(Keio Univ., Fac. of Sci. and Technol.)
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Journal Title;IEIC Technical Report (Institute of Electronics, Information and Communication Engineers)
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Journal Code:S0532B
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ISSN:0913-5685
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VOL.100;NO.533(CPSY2000 66-71);PAGE.9-15(2001)
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| Figure&Table&Reference;FIG.9, TBL.4, REF.10 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;FPGAs(Field Programmable Gate Arrays) have made possible new varieties of reconfigurable systems in which an algorithm is executed directly in hardware. However, although dynamically reconfigurable multi-context FPGAs have been implemented, it takes long time to load configuration data for reconfiguration. In order to reduce the time required for loading configuration data on multi-context FPGAs, we propose configuring a decode function on one context of the FPGA that restores the configuration data compressed in advance. Simulation results show that the decode circuits which operates with 2 times higher frequency compared to the bus clock to external configuration memory reduces the configuration time when the configuration data are well compressed. (author abst.) |
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