An Evaluation of a Context Partitioning Algorithm for Multi-Context FPGAs.
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Accession number;01A0340300
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| Title;An Evaluation of a Context Partitioning Algorithm for Multi-Context FPGAs. |
| Author;
HONDA RYO
(Osaka Univ. Graduate School of Engineering Sci., JPN)
KITAMICHI JUNJI
(Osaka Univ., Cybermedia Center, JPN)
FUNABIKI NOBUO
(Osaka Univ. Graduate School of Engineering Sci., JPN)
HIGASHINO TERUO
(Osaka Univ. Graduate School of Engineering Sci., JPN)
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Journal Title;IEIC Technical Report (Institute of Electronics, Information and Communication Engineers)
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Journal Code:S0532B
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ISSN:0913-5685
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VOL.100;NO.533(CPSY2000 66-71);PAGE.17-24(2001)
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| Figure&Table&Reference;FIG.6, TBL.2, REF.12 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;A multi-context FPGA is a kind of Dynamically Reconfigurable FPGA(DRFPGA) with better reconfiguration time-efficiency than conventional DRFPGA. In synthesis for a multi-context FPGA, we consider the context partitioning probrem. The context partitioning probrem is a step of a multi-context FPGA design flow, in which a given circuit is packed into reconfiguration units, called contexts, of a multi-context FPGA so that the reconfiguration time over head can be small. We have proposed a heuristic algorithm to solve the context partitioning problem. In this paper, we apply our algorithm to some real examples and evaluate our algorithm. (author abst.) |
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