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Accession number;01A0340302
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| Title;A Scheduling Algorithm for a Dynamic Reconfigurable System Based on Multiple FPGAs. |
| Author;
ISHITOBI TAKASHI
(Waseda Univ., Sch. of Sci. & Eng.)
TOGAWA NOZOMU
(Advanced Res. Center for Sci. and Engineering, Waseda Univ.)
YANAGISAWA MASAO
(Waseda Univ., Sch. of Sci. & Eng.)
OTSUKI TATSUO
(Waseda Univ., Sch. of Sci. & Eng.)
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Journal Title;IEIC Technical Report (Institute of Electronics, Information and Communication Engineers)
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Journal Code:S0532B
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ISSN:0913-5685
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VOL.100;NO.533(CPSY2000 66-71);PAGE.33-40(2001)
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| Figure&Table&Reference;FIG.10, TBL.4, REF.16 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;Recently, there has been proposed a dynamically reconfigurable system where a part of the system can be reconfigured in-system. In an FPGA-based dynamically reconfigurable system, a task scheduling algorithm which takes into account a reconfiguration time is required to minimize the runtime of an application running on the system. In this paper, we propose a scheduling algorithm for the dynamic reconfigurable system based on multiple FPGAs. The objective of the algorithm is to minimize the system runtime of the application. A task execution time and a processing FPGA allocation are determined under given FPGA resources and execution order of tasks. In the algorithm, we define a criterion how much the task execution time and the reconfiguration time influence delays of the system runtime of the application and we balance task delays based on the criterion by gradually reducing scheduling candinates of each task. Therefore, we can keep the delays of the system runtime of the application down by taking account of the number of reconfigurations. Experimental results demonstrate the efficiency and effectiveness of the algorithm. (author abst.) |
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