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Accession number;01A0340304
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| Title;A Discrete Cosine Transform Circuit with Dynamically Reconfigurable Digit-Serial Computation. |
| Author;
ITO KAZUHITO
(Saitama Univ.)
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Journal Title;IEIC Technical Report (Institute of Electronics, Information and Communication Engineers)
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Journal Code:S0532B
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ISSN:0913-5685
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VOL.100;NO.534(CPSY2000 72-81);PAGE.1-8(2001)
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| Figure&Table&Reference;FIG.12, REF.13 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;In the era of deep submicron technology, wire delay on an LSI chip is becoming relatively larger than operation delay. Data communication time by wire delay between processing units could be reduced and hence fast processing can be achieved if nearby processing units are dynamically reconfigured into desired operation type and execute operations on the reconfigured units. Based on the simplicity of reconfiguring digit-serial computation, we propose a compact and fast 1-D discrete cosine transfer circuit with dynamically reconfigurable digit-serial computation. An LSI chip is designed and its speed is measured by a circuit simulator. Results show the effectiveness of the proposed circuit. (author abst.) |
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