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Accession number;01A0340307
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| Title;Semi-Synchronous Clock Tree Construction Under Synchronous Circuit Design Environment. |
| Author;
ISHIJIMA SEIICHIRO
(Tokyokodai Daigakuinrikogakukenkyuka)
TAKAHASHI ATSUSHI
(Tokyokodai Daigakuinrikogakukenkyuka)
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Journal Title;IEIC Technical Report (Institute of Electronics, Information and Communication Engineers)
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Journal Code:S0532B
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ISSN:0913-5685
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VOL.100;NO.534(CPSY2000 72-81);PAGE.25-31(2001)
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| Figure&Table&Reference;FIG.8, TBL.2, REF.11 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;A circuit in which clock is not necessary distributed to all registers simultaneously, called a semi-synchronous circuit, leads to higher frequency or smaller clock tree of the circuit compared with a synchronous circuit. In this paper, we propose a design method to realize a clock tree of semi-synchronous circuit. The method constructs the clock tree making use of conventional design environment. First, it determines the outline of the clock tree structure by using the information of gate delay and determines the detail after the placement of the circuit. Next, it determines the clock schedule by using the information of delay including routing delay and realizes the semi-synchronous circuit by inserting buffers into the clock tree. We apply the proposed method to a micro processor design and find that it is easy to apply and that a faster circuit is obtained. (author abst.) |
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