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Accession number;01A0340308
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| Title;On a Technique to Eliminate False-Paths for the Statistical Static Timing Analysis. |
| Author;
TSUKIYAMA SHUJI
(Chuo Univ., Fac. of Sci. & Eng.)
TANAKA MASAKAZU
(Matsushitadenkisangyo Handotaikaihatsuhombu)
FUKUI MASAHIRO
(Matsushitadenkisangyo Handotaikaihatsuhombu)
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Journal Title;IEIC Technical Report (Institute of Electronics, Information and Communication Engineers)
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Journal Code:S0532B
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ISSN:0913-5685
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VOL.100;NO.534(CPSY2000 72-81);PAGE.33-40(2001)
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| Figure&Table&Reference;FIG.7, REF.13 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;In this paper, we present a tequnique to eliminate false-paths specified by the circuit topology in the statical static timing analysis of a CMOS combinatorial circuit. The technique can be embeded in our timing analyzer, which treats not only correlations between distributions of delays of reconvergent-paths, but also correlations between distributions of transistor delays in a logic gate and correlations between interconnect delays in a net. The method treating such correlations is used for eliminating falth-paths. (author abst.) |
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