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Accession number;01A0340310
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| Title;A Hierarchical Parallel and Distributed Placer on a PC Cluster by using Voyager. |
| Author;
WATANUKI NORIHISA
(Gunma Univ., Fac. of Eng.)
SHIRAISHI YOICHI
(Gunma Univ., Fac. of Eng.)
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Journal Title;IEIC Technical Report (Institute of Electronics, Information and Communication Engineers)
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Journal Code:S0532B
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ISSN:0913-5685
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VOL.100;NO.534(CPSY2000 72-81);PAGE.49-56(2001)
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| Figure&Table&Reference;FIG.9, TBL.3, REF.9 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;A hierarchical parallel and distributed placer based on the randomized algorithm is developed. The target of this process is the cell placement problem in the layout design for a logic VLSI chip. This process is implemented by using Java and the core of the parallel and distributed process is realized by using Voyager. In this report, the simulation on one EWS first reveals the acceleration of the cell placement process itself. Then, the actual hierarchical parallel and distributed placement is implemented on a PC cluster by using Voyager and its feasibility is checked. The acceleration itself can not yet be evaluated but the communication overhead is evaluated against some benchmark data and the problems occurred in the communication overhead is revealed. (author abst.) |
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