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Accession number;01A0340311
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| Title;An Implementation of Parallel Distributed Device Model Evaluation on Circuit Simulation. |
| Author;
SUZUKI TSUYOSHI
(Hosei Univ.)
YAGI HIROYUKI
(Hosei Univ.)
DAN RYO
(Hosei Univ.)
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Journal Title;IEIC Technical Report (Institute of Electronics, Information and Communication Engineers)
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Journal Code:S0532B
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ISSN:0913-5685
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VOL.100;NO.534(CPSY2000 72-81);PAGE.57-63(2001)
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| Figure&Table&Reference;FIG.10, TBL.4, REF.10 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;We propose a parallel distributed device model evaluation algorithm in the circuit simulation. Parallel distributed device model evaluation can speed up while maintaining accuracy, because the approach chosen to speed up SPICE is parallelizetion of device model evaluation. In this paper, we estimate the performance of this circuit simulator using the parallel distributed device model evaluation algorithm. The parallel distributed device model evaluation is able to reduce the device model evaluation to 53.5-68.15% in comparison with the original SPICE2. As a result, our circuit simulator can run 1.7 times faster than the original SPICE2 in the maximum speedup. (author abst.) |
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