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Accession number;01A0340313
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| Title;Design Optimization Method Using Digit Serial Operation for DSP Systems. |
| Author;
WATANABE YOSHIHARU
(Osaka Univ. Graduate School of Engineering Sci., JPN)
TAKEUCHI YOSHINORI
(Osaka Univ. Graduate School of Engineering Sci., JPN)
KITAJIMA AKIRA
(Osaka Univ. Graduate School of Engineering Sci., JPN)
IMAI MASAHARU
(Osaka Univ. Graduate School of Engineering Sci., JPN)
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Journal Title;IEIC Technical Report (Institute of Electronics, Information and Communication Engineers)
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Journal Code:S0532B
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ISSN:0913-5685
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VOL.100;NO.534(CPSY2000 72-81);PAGE.71-78(2001)
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| Figure&Table&Reference;FIG.9, TBL.3, REF.9 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;This paper studies DSP system architecture optimization method using digit serial operation under the throughput constraint. The proposed method can make the DSP system design considering the trade-offs between the hardware cost and the throughput which are introduced by efficient digit size conversions. Experimental results show the trade-offs between the hardware cost and the throughput and the optimum architecture of DSP system can be decided using proposal digit size conversion algorithm under the throughput constraint. (author abst.) |
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