Effect of facility for hot spot reduction of inter-level dielectric (ILD) CMP process.
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Accession number;02A0423797
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| Title;Effect of facility for hot spot reduction of inter-level dielectric (ILD) CMP process. |
| Author;
JEONG S-Y
(Daebul Univ., Chonnam, Kor)
SEO Y-J
(Daebul Univ., Chonnam, Kor)
KIM S-Y
(Anam Semiconductor Co., Inc.)
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Journal Title;Proceedings of the Symposium on Electrical and Electronic Insulating Materials and Applications in Systems
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Journal Code:G0398B
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ISSN:
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VOL.33rd;NO.;PAGE.95-98(2001)
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| Figure&Table&Reference;FIG.6, REF.9 |
| Pub. Country;Japan |
| Language;English |
| Abstract;Chemical mechanical polishing(CMP) process is widely used for global planarization of inter-level dielectric(ILD) for sub-micron technology. But the hot-spot due to partial over-polishing was generated in the edge of wafers, and became a major concern. Thus, it is very important to understand the correlation between ILD-CMP process and various facility factors of CMP equipment system. With facility shortage of deionized water(DIW) pressure, we introduced an adding purified N2(PN2) gas in polishing head cleaning station for increasing a cleaning effect. Our experimental results show that DIW pressure and PN2 gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. We estimated two factors (DIW pressure and PN2 gas) for the improvement of CMP process. Especially, we obtained a uniform planarity in patterned wafer and prohibited more than 90% of wafer edge over-polishing. Finally, we suggest that the facility factors supplied to equipment system play an important role in ILD-CMP process. (author abst.) |
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