Gate patterning for ultimate CMOS devices.
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Accession number;02A0865382
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| Title;Gate patterning for ultimate CMOS devices. |
| Author;
VALLIER L
(Lab. Technol. Microelectronique, Cnrs, Grenoble, Fra)
FOUCHER J
(Lab. Technol. Microelectronique, Cnrs, Grenoble, Fra)
PARGON E
(Lab. Technol. Microelectronique, Cnrs, Grenoble, Fra)
DETTER X
(Lab. Technol. Microelectronique, Cnrs, Grenoble, Fra)
CUNGE G
(Lab. Technol. Microelectronique, Cnrs, Grenoble, Fra)
JOUBERT O
(Lab. Technol. Microelectronique, Cnrs, Grenoble, Fra)
SONGLIN X
(Applied Materials, Ca, Usa)
LILL T
(Applied Materials, Ca, Usa)
PODLESNIK D
(Applied Materials, Ca, Usa)
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Journal Title;Proc Int Symp Dry Process
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Journal Code:Y0378B
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ISSN:
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VOL.2nd;NO.;PAGE.93-100(2002)
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| Figure&Table&Reference;FIG.10, REF.7 |
| Pub. Country;Japan |
| Language;English |
| Abstract;We address some of the plasma issues encounter for ultimate Silicon gate patterning that should be fixed in order to establish the long term viability of plasma processes in Integrated Circuits manufacturing. For sub-100nm gate dimensions, one of the main issue is to precisely control the shape of the etched feature. This requires a detailed knowledge of the various physico-chemical mechanisms involved in plasma etching and deposition, as advanced plasma processes are using both at the same time to tailor the gate stack profile (including the resist pattern) just by tuning the plasma operating parameters and the gas chemistry to independently control the vertical and the lateral etch-rates in dense and isolated pattern areas. (author abst.) |
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