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Accession number;03A0133856
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| Title;A Hardware Overview of SX-6 and SX-7 Supercomputer. |
| Author;
KITAGAWA K
(Nec Corp.)
TAGAYA S
(Nec Corp.)
HAGIHARA Y
(Nec Corp.)
KANOH Y
(Nec Corp.)
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Journal Title;NEC Res Dev
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Journal Code:G0138A
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ISSN:0547-051X
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VOL.44;NO.1;PAGE.2-7(2003)
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| Figure&Table&Reference;FIG.11, TBL.2, REF.4 |
| Pub. Country;Japan |
| Language;English |
| Abstract;NEC has been developing vector supercomputers since 1983 to meet the growing demand for high performance computing (HPC), especially in scientific and engineering fields. SX-6 and SX-7 were developed to meet the limitless requirement for computation. A single-chip vector CPU including eight vector pipelines and a scalar unit was developed for SX-6 and SX-7. Vector pipeline and scalar unit design will be discussed. To achieve high performance and realize high sustained performance, a combination of vector type processor and high bandwidth architecture was exploited. For more performance a multi-node system was developed. A single-stage crossbar switch was developed to achieve high bandwidth and to minimize the delay because of contention. As a result, theoretical peak performance of 64GFLOPS was achieved for 8 CPU, and up to 8TFLOPS for a multimode system. To develop the low cost and high-performance supercomputer SX-6, all functions of the vector CPU are integrated on a single die. This was achieved by 0.15.MU.m Cu interconnection CMOS technology. (author abst.) |
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