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Accession number;03A0493402
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| Title;Development of CoC (Chip-on-Chip) Interconnection Technology in Hyperfine Pitch |
| Author;
NISHIYAMA T
(Nec Corp.)
TAGO M
(Nec Corp.)
ISOZAKI S
(Nec Electronics Corp.)
MORISHITA Y
(Nec Electronics Corp.)
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Journal Title;NEC Res Dev
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Journal Code:G0138A
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ISSN:0547-051X
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VOL.44;NO.3;PAGE.231-234(2003)
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| Figure&Table&Reference;FIG.8, TBL.3, REF.2 |
| Pub. Country;Japan |
| Language;English |
| Abstract;CoC (Chip-on-Chip) Interconnection Technology, an indispensable future technology, which comprises high performance SiP (System in a Package), has been developed. Gold bumps, electroplated in 50.MU.m-pitch on both LSI chips, were connected in the thermo-compression bonding process. Heat was provided only from the daughter chip side, and the mother chip was held at less than 100 degrees in consideration of manufacturing process. We investigated the connectivity and the electrical characteristic changes of transistors placed directly under bumps. By optimizing the process condition, good junction without damage was achieved. (author abst.) |
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