Sequential Speed Estimation Algorithm for High Speed Mobile Terrestrial Digital Television Broadcasting Receiver
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Accession number;04A0178096
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| Title;Sequential Speed Estimation Algorithm for High Speed Mobile Terrestrial Digital Television Broadcasting Receiver |
| Author;
TANIGUCHI TSUKASA
(Advanced Inst. Sci. and Technol., Nara)
NAGAI NORIKAZU
(Advanced Inst. Sci. and Technol., Nara)
OKADA MINORU
(Advanced Inst. Sci. and Technol., Nara)
YAMAMOTO HIDEICHI
(Advanced Inst. Sci. and Technol., Nara)
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Journal Title;IEIC Technical Report (Institute of Electronics, Information and Communication Engineers)
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Journal Code:S0532B
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ISSN:0913-5685
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VOL.103;NO.542(ITS2003 43-48);PAGE.27-32(2004)
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| Figure&Table&Reference;FIG.11, TBL.1, REF.5 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;Mobile reception for terrestrial digital television broadcasting is difficult because the transmission performance is severely degraded due to fast time variations of the propagation channel. To solve this problem, some of the authors have proposed compensation method for fast time variations of the propagation channel, in which array antenna is exploited to interpolate the received signal on space domain so as to make the reception point virtually stationary against the ground. In this method, two compensators having different speed estimate are operated simultaneously. By observing the received signal quality after compensation, the speed estimate is updated so as to improve the received signal quality. Consequently, virtually stationary reception point can be calculated. However, the receiver is highly complex because two receiver chains are required. Therefore, in this report, we propose a novel speed estimation method where speed estimation is performed sequentially, by changing the speed estimate every other received symbol according to the observed signal quality after the compensation. Thus, only one compensator and one receiver chain are required. Computer simulation results clarified that almost equal convergence characteristics to that of the conventional method is achieved by our proposed method while reducing the hardware complexity. (author abst.) |
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