Power Consumption Reduction through Combining Pipeline Stage Unification and DVS
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Accession number;07A0176828
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| Title;Power Consumption Reduction through Combining Pipeline Stage Unification and DVS |
| Author;
SHIMADA HAJIME
(Kyoto Univ., Graduate School of Informatics, JPN)
ANDO HIDEKI
(Nagoya Univ., Graduate School of Engineering, JPN)
SHIMADA TOSHIO
(Nagoya Univ., Graduate School of Engineering, JPN)
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Journal Title;IPSJ Transactions on Database
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Journal Code:Z0778A
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ISSN:0387-5806
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VOL.48;NO.SIG3(ACS17);PAGE.75-87(2007)
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| Figure&Table&Reference;FIG.7, TBL.4, REF.36 |
| Pub. Country;Japan |
| Language;Japanese |
| Abstract;Recent mobile processors are required to exhibit both low-power consumption and high performance. To satisfy these requirements, we proposed pipeline stage unification (PSU), and showed that it can reduce energy consumption than that of dynamic voltage scaling (DVS) which is currently employed. However, DVS and PSU are not exclusive techniques, and so further reduction of power consumption can be achieved through combining them. This paper proposes a hybrid control mechanism which combines DVS and PSU to reduce power consumption more. This mechanism adapts the number of unifying stages, clock frequency, and supply voltage according to the throughput that the system requires, and consequently it reduces power consumption more than standalone DVS and standalone PSU. We evaluated our mechanism with various target throughputs. Our evaluation results show that our mechanism reduces power consumption by a maximum of 14% compared to the standalone DVS or by a maximum of 28% compared to the standalone PSU. (author abst.) |
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